Hybrid bonding technology for stacking integrated circuits

ABSTRACT

A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, the 3D IC comprises a first IC die comprising a first substrate, a first interconnect structure disposed over the first substrate, and a first through substrate via(TSV) disposed through the first substrate. The 3D IC further comprises a second IC die comprising a second substrate, a second interconnect structure disposed over the second substrate, and a second TSV disposed through the second substrate. The 3D IC further comprises a bonding structure arranged between back sides of the first IC die and the second IC die opposite to corresponding interconnect structures and bonding the first IC die and the second IC die. The bonding structure comprises conductive features disposed between and electrically connecting the first TSV and the second TSV.

REFERENCE TO RELATED APPLICATIONS

This Application is a Continuation of U.S. application Ser. No. 16/902,539, filed on Jun. 16, 2020, which is a Continuation of U.S. application Ser. No. 15/998,455, filed on Aug. 15, 2018 (now U.S. Pat. No. 10,727,205, issued on Jul. 28, 2020). The contents of the above-referenced Patent Applications are hereby incorporated by reference in their entirety.

BACKGROUND

The semiconductor industry has continually improved the processing capabilities and power consumption of integrated circuits (ICs) by shrinking the minimum feature size. However, in recent years, process limitations have made it difficult to continue shrinking the minimum feature size. The stacking of two-dimensional (2D) ICs into three-dimensional (3D) ICs has emerged as a potential approach to continue improving processing capabilities and power consumption of ICs.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1-3 illustrate a series of cross-sectional views of a method for manufacturing a three-dimensional (3D) integrated circuit (IC) including a back to back bonding structure according to some embodiments.

FIGS. 4 and 5 illustrate cross-sectional views of a 3D IC including a back to back bonding structure according to some alternative embodiments.

FIGS. 6-8 illustrate varies regional cross-sectional views of a 3D IC including a back to back bonding structure according to some additional embodiments.

FIGS. 9-14 illustrate cross-sectional views of a 3D IC including a front to back bonding structure according to some embodiments.

FIGS. 15-19 illustrate a series of cross-sectional views of a method for manufacturing a three-dimensional (3D) integrated circuit (IC) including a front to back bonding structure according to some embodiments.

FIG. 20 illustrates a flow diagram of a method of forming an integrated circuit device according to some embodiments.

DETAILED DESCRIPTION

The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper”, and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device or apparatus in use or operation in addition to the orientation depicted in the figures. The device or apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Even more, the terms “first”, “second”, “third”, “fourth”, and the like are merely generic identifiers and, as such, may be interchanged in various embodiments. For example, while an element (e.g., a conductive wire) may be referred to as a “first” element in some embodiments, the element may be referred to as a “second” element in other embodiments.

A three-dimensional (3D) integrated circuit (IC) comprises a plurality of two-dimensional (2D) IC dies one stacked and bonded on another. One of the methods to manufacture the 3D IC includes bonding a first IC die and a second IC die face to face first. The first and second IC dies comprise respective semiconductor substrates, respective interconnect structures between the semiconductor substrates. The interconnect structures comprise alternating stacks of metal lines (e.g., horizontal routing) and metal vias (e.g., vertical routing). The face to face bonding means having respective bonding structures of the first IC die and the second IC die disposed between the interconnect structures. Then, a thinning process may be performed from a back side of the second IC die to thin the second substrate, and a third IC die is bonded to the second IC die. The third IC die can be bonded to the back side of the second IC die from a front side, i.e., forming a front to back bonding, and exposing a semiconductor substrate from a back side of the third IC die. The third IC die can also be bonded to the back side of the second IC die from a back side, i.e., forming a back to back bonding, and exposing an interconnect structure from a front side of the third IC die. Then, a fourth IC die can be continued to be bonded to the exposed side of the third IC die. As the technology develops and the circuitry becomes more complicated, more 2D IC dies can be stacked together. When the 3D IC includes more than three or five stacked 2D IC dies, manufacturing period becomes very long. There is a need to improve the efficiency and shorten the manufacturing period.

In view of the foregoing, various embodiments of the present application are directed towards a “parallel” method to manufacture a 3D IC and to improve the manufacturing period. Various embodiments of an improved hybrid bonding structure are also disclosed which can be formed in a more timely manner. Referring to FIGS. 1-3 for example, multiple dies such as four IC dies 10, 20, 30, and 40 are vertically stacked together to form a 3D IC. In some embodiments, the multiple dies can be divided in two or more sub-groups for bonding and then be bonded together. For example, a first IC die 10 and a second IC die can be bonded together, and a third IC die 30 and a fourth IC die 40 can be bonded together concurrently or at least having processing time overlapped. Then the bonded sub-groups can be bonded together. Compared to a sequential manufacturing process where the multiple dies are bonded together on after another, this “parallel” manufacturing process shortens the whole manufacturing period. Some example bonding processes and bonding structures are disclosed below.

As shown in FIG. 1, a first IC die 10 and a second IC die 20 may be bonded together face to face by a first bonding structure 132. The first IC die 10 comprises a first substrate 100 and a first interconnect structure 104 over the first substrate 100. The substrate 100, and other substrates described below, may include a semiconductor wafer, a portion of a semiconductor wafer, a semiconductor die, or other applicable substrates. The first interconnect structure 104 comprises a first plurality of metal lines 106 and a first plurality of metal vias 108 alternatingly stacked in a first ILD layer 110 (interlayer dielectric layer). The second IC die 20 comprises a second substrate 200 and a second interconnect structure 204 over the second substrate. The second interconnect structure 204 comprises a second plurality of metal lines 206 and a second plurality of metal vias 208 alternatingly stacked in a second ILD layer 210. The bonding process may be a hybrid bonding process including conductor-to-conductor bonding and dielectric-to-dielectric bonding processes. The first bonding structure 132 comprises a first portion 132 a contacting the first interconnect structure 104 and a second portion 132 b contacting the second interconnect structure 204. The first bonding structure 132 may comprise respective bonding dielectric layers 120, 220, respective redistribution layers 114, 214, dummy respective redistribution layers 116, 216, and respective bonding contacts 112, 212. The redistribution layers 114, 214 and the dummy respective redistribution layers 116, 216 are sunken into the bonding dielectric layers 120, 220 and directly contact each other to define a conductor-to-conductor interface. The redistribution layers 114, 214, dummy redistribution layers 116, 216, and other redistribution layers and dummy redistribution layers described below are made for bonding purposes. The redistribution layers and dummy redistribution layers may have rectangular, rounded or other applicable shapes from a top view. The redistribution layers and dummy redistribution layers may be made of Cu, Al, W, Au, Ti, Pt, Co, another suitable material, or a combination thereof. The bonding dielectric layers 120, 220, and other the bonding dielectric layers described below, may be made of silicon oxide, silicon oxynitride, silicon nitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-k material, another suitable material, or a combination thereof. The bonding dielectric layers 120, 220, and other the bonding dielectric layers described below, may be deposited using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a spin-on process, another applicable process, or a combination thereof. The bonding dielectric layers 120, 220 may be in direct contact with each other to define a dielectric-to-dielectric interface that may be aligned with a conductor-to-conductor interface. The bonding contacts 112, 212 extend respectively from the redistribution layers 114, 214 to the interconnect structures 104, 204. Then, the second substrate 200 is thinned from a back side to prepare for a subsequent bonding process. The thinning process may comprise a chemical mechanical polishing (CMP) process, and/or other thinning techniques. A second TSV (through substrate via) 218 is formed through the second substrate 200. The second TSV 218 may be formed by forming a through substrate trench opening 1602 through the second substrate 200 into the second ILD layer 210 to expose one of the metal lines 206 of the second interconnect structure 204 followed by filling a conductive material into the through substrate trench opening 1602. The second TSV 218 may have a top surface coplanar or higher than a top surface of the second substrate 200.

Similarly, as shown in FIG. 2, a third IC die 30 and a fourth IC die 40 may be bonded together face to face by a second bonding structure 232. The third IC die comprises a third substrate 300 and a third interconnect structure 304 over the third substrate. The third interconnect structure 304 comprises a third plurality of metal lines 306 and a third plurality of metal vias 308 alternatingly stacked in a third ILD layer 310. The fourth IC die 40 comprises a fourth substrate 400 and a fourth interconnect structure 404 over the fourth substrate. The fourth interconnect structure 404 comprises a fourth plurality of metal lines 406 and a fourth plurality of metal vias 408 alternatingly stacked in a fourth ILD layer 410. The second bonding structure 232 comprises a first portion 232 a contacting the third interconnect structure 304 and a second portion 232 b contacting the fourth interconnect structure 404. The second bonding structure 232 may also comprise respective bonding dielectric layers 320, 420, respective redistribution layers 314, 414, dummy respective redistribution layers 316, 416, and respective bonding contacts 312, 412. The redistribution layers 314, 414 and the dummy respective redistribution layers 316, 416 are sunken into the bonding dielectric layers 320, 420 and directly contact each other. The bonding contacts 312, 412 extend respectively from the redistribution layers 314, 414 to the interconnect structures 304, 404. Then, the third substrate 300 is thinned from a back side to prepare for a subsequent bonding process. A third TSV (through substrate via) 318 is formed through the third substrate 300.

As shown in FIG. 3, the second substrate 200 and the third substrate 300 are bonded together by a third bonding structure 332 through the second TSV 218 and the third TSV 318. The processes shown in FIG. 2 can be performed at the same time or in a time frame at least overlapped with performing the processes shown in FIG. 1. Then the work pieces from the processes of FIG. 1 and FIG. 2 can be bonded together. In this way, the manufacturing time period needed can be significantly reduced. The third bonding structure 332 may be different from the first bonding structure 132 or the second bonding structure 232. In some embodiments, the second TSV 218 is in direct contact with the third TSV 318, and the second substrate 200 is in direct contact with the third substrate 300. The second TSV 218 and the third TSV 318 may have sidewalls tilted in opposite directions. In a direction from top to bottom of FIG. 3, an upper part of the third TSV 318 closer to a bonding interface of the third bonding structure 332 is outwardly tilted, while an upper part of the second TSV 218 closer to a bonding interface of the third bonding structure 332 is inwardly tilted. The second TSV 218 and the third TSV 318 may have substantially same lateral dimensions.

The IC dies 10, 20, 30, 40 may respectively comprises one or more device elements 102, 202, 302, 402 distributed within the substrates 100, 200, 300, 400, and electrically coupled to one another with conductive paths defined by the interconnect structures 104, 204, 304, 404 and the bonding structures 132, 232, 332. The device elements 102, 202, 302, 402 may be, for example, MOSFETs, IGFETS, MIM capacitors, flash memory cells, or the like.

FIG. 4 shows a cross-sectional view of a 3D IC according to some additional embodiments. Disposed within bonding dielectric layers 220, 320 and between the second TSV 218 and the third TSV 318, the third bonding structure 332 may further comprise a pair of redistribution layers 224, 324 directly bonded to each other and a pair of dummy redistribution layers 226, 326 directly bonded to each other. A pair of bonding contacts 222, 322 is respectively coupled to the redistribution layers 224, 324. A second bonding metal line 236 and a second bonding metal via 238 may be disposed between the second TSV 218 and the redistribution layer 224. A third bonding metal line 336 and a third bonding metal via 338 may be disposed between the third TSV 318 and the redistribution layer 324. The bonding metal lines 236, 336 and the bonding metal vias 238, 338 provide additional routing flexibilities.

FIG. 5 shows a cross-sectional view of a 3D IC according to some additional embodiments. The pair of redistribution layers 224, 324 may be directly contact the respective second bonding metal line 236 and third bonding metal line 336. By omitting the pair of bonding contacts 222, 322 shown in FIG. 4 from the third bonding structure 332, the manufacturing process is simplified and manufacturing time is shortened.

FIGS. 6-8 show varies regional cross-sectional views of a back to back bonding structure of a 3D IC. It is noted that the disclosed bonding structures are labeled as ‘332’, and can be some additional embodiments that can incorporate into or replace the third bonding structure 332 shown in FIG. 3. The disclosed bonding structures can also stand alone or incorporate into other applicable 3D ICs. As shown in FIG. 6, a set of redistribution layer 324, bonding metal line 336, and bonding metal via 338 can be disposed within a bonding dielectric layer 320 and between the second TSV 218 and the third TSV 318. Sidewalls of the redistribution layer 324, the bonding metal line 336, and the bonding metal via 338 can be titled in the same direction (e.g. all outwardly as shown in the figure), and be same with that of the third TSV 318. As shown in FIG. 7, a set of bonding contact 702, bonding metal line 336, and bonding metal via 338 can be disposed within the bonding dielectric layer 320 and between the second TSV 218 and the third TSV 318. Sidewalls of the bonding contact 702, the bonding metal line 336, and the bonding metal via 338 can be titled in the same direction (e.g. all outwardly as shown in the figure), and be same with that of the third TSV 318. As shown in FIG. 8, a set of bonding metal line 336, and bonding metal via 338 can be disposed within the bonding dielectric layer 320 and directly contact the second TSV 218 and the third TSV 318. Sidewalls of the bonding metal line 336, and the bonding metal via 338 can be titled in the same direction (e.g. all outwardly as shown in the figure), and be same with that of the third TSV 318. The bonding metal line 336 and bonding metal via 338 provide additional routing flexibility. By omitting the bonding contacts or the redistribution layers of the previous embodiments, the manufacturing time period is further reduced.

FIGS. 9-14 show cross-sectional views of a 3D IC including a front to back bonding structure according to some embodiments. In FIG. 9, a first IC die 10 and a second IC die 20 may be bonded together face to face by a first bonding structure 132. The first IC die 10 comprises a first substrate 100 and a first interconnect structure 104 over the first substrate 100. The first interconnect structure 104 comprises a first plurality of metal lines 106 and a first plurality of metal vias 108 alternatingly stacked in a first ILD layer 110 (interlayer dielectric layer). The second IC die 20 comprises a second substrate 200 and a second interconnect structure 204 disposed at a front side 904 over the second substrate 200. The second interconnect structure 204 comprises a second plurality of metal lines 206 and a second plurality of metal vias 208 alternatingly stacked in a second ILD layer 210. The first bonding structure 132 comprises a first portion 132 a contacting the first interconnect structure 104 and a second portion 132 b contacting the second interconnect structure 204. The first bonding structure 132 may comprise respective bonding dielectric layers 120, 220, respective redistribution layers 114, 214, dummy respective redistribution layers 116, 216, and respective bonding contacts 112, 212. The redistribution layers 114, 214 and the dummy respective redistribution layers 116, 216 are sunken into the bonding dielectric layers 120, 220 and directly contact each other. The bonding contacts 112, 212 extend respectively from the redistribution layers 114, 214 to the interconnect structures 104, 204. A third IC die 30 is bonded to a back side 902 of the second IC die 20 by a third bonding structure 332. The third IC die 30 comprises a third substrate 300 and a third interconnect structure 304 over the third substrate. The third interconnect structure 304 comprises a third plurality of metal lines 306 and a third plurality of metal vias 308 alternatingly stacked in a third ILD layer 310. The third bonding structure 332 comprises a second TSV 218 disposed through the second substrate 200 and a bonding contact 322 bonded directly to the second TSV 218. The bonding contact 322 connects the second TSV 218 to one of the metal lines 306 of the third IC die 30 closest to the second IC die 20. The second TSV 218 and the bonding contact 322 may have sidewalls tilted in opposite directions. The bonding contact 322 has a lateral dimension smaller than that of the second TSV 218. The bonding contact 322 may be formed by forming a bonding dielectric layer 320 over the third IC die 30 prior to bonding the third IC die 30 to the second IC die 20. Then, a contact hole is formed through the bonding dielectric layer 320 to expose one of the metal lines 306 of the third interconnect structure 304 followed by filling a conductive material into the contact hole. Then, the third IC die 30 is flipped upside down to bond the bonding contact 322 directly to the second TSV 218 may have a top surface coplanar or higher than a top surface of the second substrate 200. A dielectric liner 230 can be formed on the second substrate 200 along the second TSV 218 and the back side 902 of the second IC die 20 and bonded to the bonding dielectric layer 320.

FIG. 10 shows a cross-sectional view of a 3D IC according to some additional embodiments. In FIG. 10, the second IC die 20 comprises the second TSV 218 and a bonding contact 222 disposed directly on the second TSV 218. The second TSV 218 and the bonding contact 322 may have sidewall tilted in the same direction (i.e. tilted inwardly as shown in the figure). The bonding contact 222 is bonded to one of the metal lines 306 of the third IC die 30 closest to the second IC die 20. The bonding contact 222 may be formed by forming a bonding dielectric layer 220 over the second IC die 20 prior to bonding the second IC die 20 to the third IC die 30. Then, a contact hole is formed through the bonding dielectric layer 220 to expose second TSV 218 followed by filling a conductive material into the contact hole. Then, the bonding contact 222 is bonded directly to one of the metal lines 306 of the third interconnect structure 304.

FIG. 11 shows a cross-sectional view of a 3D IC according to some additional embodiments. In FIG. 11, the second TSV 218 of the third bonding structure 332 is disposed through the second substrate 200 and bonded directly to one of the metal lines 306 of the third IC die 30 closest to the second IC die 20. The second TSV 218 and the metal lines 306 may have sidewalls tilted in opposite directions. The second TSV 218 has a lateral dimension smaller than a lateral dimension (e.g. a length) of the metal lines 306. A dielectric liner 230 can be formed on the second substrate 200 along the second TSV 218 and the back side of the second IC die 20 and bonded to the third ILD layer 310. The dielectric liner 230 may be in direct contact with the metal lines 306 of the third IC die 30 closest to the second IC die 20. By omitting the bonding contacts of the previous embodiments, the manufacturing time period is further reduced.

FIG. 12 shows a cross-sectional view of a 3D IC according to some additional embodiments. In FIG. 12, a bonding redistribution layer 324 and a bonding contact 322 are surrounded by a bonding dielectric layer 320, disposed on the third interconnect structure 304, and electrically coupled to one of the metal lines 306 of the third IC die 30 closest to the second IC die 20. The second TSV 218 is disposed through the second substrate 200 and bonded directly to the bonding redistribution layer 324. The second TSV 218 and the bonding redistribution layer 324 may have sidewalls tilted in opposite directions. The second TSV 218 has a lateral dimension greater than that of the bonding redistribution layer 324. A dielectric liner 230 can be formed on the second substrate 200 along the second TSV 218 and the back side of the second IC die 20 and bonded to the third ILD layer 310. The dielectric liner 230 may be in direct contact with the bonding redistribution layer 324 and the bonding dielectric layer 320. By omitting forming a bonding redistribution layer and a bonding contact attached to the second substrate, the manufacturing time period is reduced. The bonding redistribution layer 324 and the bonding contact 322 may be formed by forming the bonding dielectric layer 320 over the third IC die 30 prior to bonding the third IC die 30 to the second IC die 20. Then, a contact hole is formed through the bonding dielectric layer 320 to expose one of the metal lines 306 of the third interconnect structure 304, and a trench opening is formed within an upper portion of the bonding dielectric layer overlying the contact hole. A conductive material is filled in the contact hole and the trench opening. Then, the third IC die 30 is flipped upside down to bond the redistribution layer 324 directly to the second TSV 218. Prior to the bonding process, the dielectric liner 230 can be formed on the second substrate 200 along the second TSV 218 and the back side of the second IC die 20, which can be adhered to the bonding dielectric layer 320 during the bonding process.

FIG. 13 shows a cross-sectional view of a 3D IC according to some additional embodiments. In FIG. 13, the second TSV 218 of the second IC die 20 and the metal lines 306 of the third IC die 30 are electrically coupled through a second bonding contact 222 surrounded by a second bonding dielectric layer 220 and a third bonding contact 322 surrounded by a third bonding dielectric layer 320. The second bonding contact 222 and the third bonding contact 322 may be bonded together and may have sidewalls tilted in opposite directions. The second bonding dielectric layer 220 can be adhered to the third bonding dielectric layer 320 during the bonding process.

FIG. 14 shows a cross-sectional view of a 3D IC according to some additional embodiments. In FIG. 14, a bonding redistribution layer 224 and a bonding contact 222 are surrounded by a bonding dielectric layer 220, disposed on the second substrate 200, and electrically coupled to the second TSV 218. The bonding redistribution layer 224 is bonded directly to one of the metal lines 306 of the third IC die 30 closest to the second IC die 20. The metal line 306 and the bonding redistribution layer 224 may have sidewalls tilted in opposite directions. The bonding redistribution layer 224 and the bonding contact 222 may be formed by forming the bonding dielectric layer 220 over the second IC die 20 prior to bonding the third IC die 30 to the second IC die 20. Then, a contact hole is formed through the bonding dielectric layer 220 to expose the second TSV 218, and a trench opening is formed within an upper portion of the bonding dielectric layer 220 overlying the contact hole. A conductive material is filled in the contact hole and the trench opening to form the bonding contact 222 and the bonding redistribution layer 224. Then, the third IC die 30 is bonded to the redistribution layer 224. The third ILD layer 310 can be adhered to the bonding dielectric layer 220 during the bonding process.

With reference to FIGS. 15-19, a series of cross-sectional views 1500-1900 illustrate some embodiments of a method for manufacturing a 3D IC having a plurality of 2D IC vertically stacked together.

As illustrated by the cross-sectional view 1500 of FIG. 15, a first IC die 10 and a second IC die 20 are formed and bonded together. Various device elements 102 are formed in the first substrate 100. Examples of the device elements 102 include transistors, diodes, memory devices or other suitable elements. Various processes may be used to form the device elements 102 including deposition, etching, implantation, photolithography, annealing, and/or other suitable processes. A first interconnect structure 104 is formed on the first substrate 100 overlying the device elements 102. The first interconnect structure 104 includes a first plurality of metal lines 106 and a first plurality of metal vias 108 alternatingly stacked in a first ILD layer 110 (interlayer dielectric layer). The first ILD layer 110 may include multiple dielectric sub-layers. The formation of the first interconnect structure 104 may involve multiple deposition, patterning, and planarization processes. The planarization processes may include chemical mechanical polishing (CMP) processes. In some embodiments, a planarization process is performed such that the top surfaces of some of the metal lines 106 are exposed and substantially coplanar with the top surface of the first ILD layer 110. A first bonding dielectric layer 120 is formed on the first interconnect structure 104, and a first bonding contact 112, a first redistribution layer 114, and a first dummy redistribution layer 116 can be formed sunken into the first bonding dielectric layer 120. For simplicity reason, it is not repeated here, but a second IC die 20 can be formed in a similar manner as forming the first IC die 10. The second IC die 20 comprises a second substrate 200 and a second interconnect structure 204 over the second substrate. The second interconnect structure 204 comprises a second plurality of metal lines 206 and a second plurality of metal vias 208 alternatingly stacked in a second ILD layer 210. A second bonding contact 212, a second redistribution layer 214, and a second dummy redistribution layer 216 can be formed sunken into a second bonding dielectric layer 220 and overlying the second interconnect structure 204. The bonding process may be a hybrid bonding process including conductor-to-conductor bonding of the redistribution layers 114, 214 and the dummy redistribution layers 116, 216 and dielectric-to-dielectric bonding of the bonding dielectric layers 120, 220.

As illustrated by the cross-sectional view 1600 of FIG. 16 and the cross-sectional view 1700 of FIG. 17, a second TSV (through substrate via) 218 is formed through the second substrate 200. In FIG. 16, the second substrate 200 is firstly thinned from a back side. The thinning process may comprise a chemical mechanical polishing (CMP) process, and/or other thinning techniques. A through substrate trench opening 1602 is formed through the second substrate 200 into the second ILD layer 210 to expose one of the metal lines 206 of the second interconnect structure 204 followed by filling a conductive material into the through substrate trench opening. In some embodiments, a photolithography process and an etching process are used to form the through substrate trench opening 1602. In some embodiments, the sidewalls of the through substrate trench opening 1602 are substantially perpendicular to the top surface of the substrate 200. In some other embodiments, the through substrate trench opening 1602 has slanted or tilted sidewalls. In some embodiments, the trench gradually becomes narrower as the etching process goes deeper, i.e., the trench is inwardly tilted. It is appreciated that other connection structures may have same tilting features for better filling. For example, from a front side of the second IC die 20, the metal lines 206, the metal vias 208, the redistribution layers 214, the dummy redistribution layers 216, and the bonding contacts 212 respectively become narrower from an upper side away from the second substrate 200 to a lower side closer to the second substrate 200, i.e., outwardly titled as shown in FIG. 16 (meaning the feature becomes wider from upper to lower direction of the FIG. 16). From a front side of the first IC die 10, the metal lines 106, the metal vias 108, the redistribution layers 114, the dummy redistribution layers 116, and the bonding contacts 112 respectively become narrower from an upper side away from the first substrate 100 to a lower side closer to the first substrate 100, i.e., inwardly titled as shown in FIG. 16 (meaning the feature becomes narrower from upper to lower direction of the FIG. 16). A dielectric liner 230 can be formed on the back side of the second IC die 20 and along the through substrate trench opening 1602 between the conductive material and the second substrate 200. The conductive material may be formed of, for example, aluminum, copper, aluminum copper, some other conductive material, a combination of the foregoing, or the like. The conductive material may, for example, be formed by vapor deposition, atomic layer deposition, electrochemical planting, some other growth or deposition process, or a combination of the foregoing. In FIG. 17, an excessive portion of the conductive material is etched back and removed to form the second TSV 218. The second TSV 218 may have a top surface coplanar with that of the dielectric liner 230. The second TSV 218 may also have an upper or top surface aligned with an upper or top surface of the second substrate 200 if the dielectric liner 230 is not presented or is removed from the back side of the second substrate 200. The etch back process may include a planarization process, for example, a CMP process.

As illustrated by the cross-sectional view 1800 of FIG. 18, a redistribution layer 224, a dummy redistribution layer 226, and a bonding contact 222 are formed within a second bonding dielectric layer 220. Still using the definition described in FIG. 16, from a back side of the second IC die 20, the redistribution layers 224, the dummy redistribution layers 226, and the bonding contacts 222 respectively become narrower from an upper side away from the second substrate 200 to a lower side closer to the second substrate 200, i.e., inwardly titled as shown in FIG. 18 (meaning the feature becomes narrower from upper to lower direction of the FIG. 18). The bonding redistribution layer 224 and the dummy redistribution layer 226, and the bonding contact 322 may be formed by forming a plurality of contact holes through the bonding dielectric layer 320 to reach on the second TSV 218. Then, a plurality of trench openings is formed within an upper portion of the second bonding dielectric layer 220. Some of the trench openings overly the contact hole. A conductive material is filled in the contact hole and the trench opening followed by a planarization process. It is appreciated that though a via-first dual-damascene like process is described above to form the redistribution layer 224 and the bonding contact 222, other processes such as trench-first dual damascene process or single damascene process can also be used.

As illustrated by the cross-sectional view 1900 of FIG. 19, a third IC die 30 is bonded to the back side of the second IC die 20. The third IC die 30 may comprise a third substrate 300 and a third interconnect structure 304 over the third substrate 300. The third interconnect structure 304 comprises a third plurality of metal lines 306 and a third plurality of metal vias 308 alternatingly stacked in a third ILD layer 310. The bonding redistribution layer 224 and the dummy redistribution layer 226 are bonded to metal lines 306 of the third IC die 30 closest to the second IC die 20. A bonding interface of third IC die 30 and the second IC die 20 can be detected by the tilting directions of the features' sidewalls. Still using the definition described in FIG. 16, from a front side of the third IC die 30, the metal lines 306 and the metal vias 308 are outwardly titled as shown in FIG. 19 (meaning the feature becomes wider from upper to lower direction of the FIG. 19). Thus, sidewalls of the metal lines 306 and the metal vias 308 are tilted in a direction (outward) opposite to the tilting direction (inward) of the bonding redistribution layer 224 and the dummy redistribution layer 226. Though not shown in the figures, barrier liners may be formed along respective sidewall and bottom surfaces of the metal lines 306, the redistribution layers 224 and the dummy redistribution layers 226, but not along the bonding interface where the metal lines 306 are bonded to the redistribution layers 224 or the dummy redistribution layers 226.

It is noted that FIGS. 15-19 illustrate some example manufacturing processes to form some embodiments of a 3D IC having a structure corresponding to FIG. 14. It is appreciated that the processes shown in FIGS. 15-19 can be altered to form some other embodiments of a 3D IC as shown in other figures. For example, the third IC die 30 may be flipped upside down to be back-side bonded to the second IC die 20 to form structures shown in FIGS. 4-8; the bonding dielectric layer 320 and the bonding contact 322 can be formed on the third interconnect structure 304 prior to bonding the third IC die 30 to the second IC die 20 to prepare for the structure shown in FIG. 9; the redistribution layer 224 can be omitted from forming on the second interconnect structure 204 to prepare the second IC die 20 for the structure shown in FIG. 10, the bonding contact 222 can be further omitted from forming on the second interconnect structure 204 to prepare the second IC die 20 for the structure shown in FIG. 11, and so on. It is appreciated the components formed between two IC dies help to provide better (e.g. flatter) bonding interface, and additional metal lines helps to provide more flexible routing. However, extra layers of bonding components are process time consuming. As the planarization process improves, those layers can be reduced or omitted, which would reduce process period time.

FIG. 20 shows some embodiments of a flow diagram of a method 2000 of forming an integrated circuit device. Although method 2000 is described in relation to FIGS. 1-3, it will be appreciated that the method 2000 is not limited to such structures disclosed in FIGS. 1-3, but instead may stand alone independent of the structures disclosed in FIGS. 1-3. Similarly, it will be appreciated that the structures disclosed in FIGS. 1-3 are not limited to the method 2000, but instead may stand alone as structures independent of the method 2000. Also, while disclosed methods (e.g., method 2000) are illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

At 2002, a first IC die and a second IC die are provided and bonded. The first IC die comprises a first substrate and a first interconnect structure over the first substrate. The second IC die comprises a second substrate and a second interconnect structure over the second substrate. The second IC die is bonded to the first IC die by a first bonding structure comprising a first portion contacting the first interconnect structure and a second portion contacting the second interconnect structure.

At 2004, the second substrate is thinned. A second TSV is formed through the second substrate. For example, FIG. 1 shows some embodiments of a cross-sectional view corresponding to act 2002 and act 2004.

At 2006, a third IC die and a fourth IC die are provided and bonded. The third IC die comprises a third substrate and a third interconnect structure over the third substrate. The fourth IC die comprises a fourth substrate and a fourth interconnect structure over the fourth substrate. The fourth IC die is bonded to the third IC die by a second bonding structure comprising a first portion contacting the third interconnect structure and a second portion contacting the fourth interconnect structure.

At 2008, the third substrate is thinned. A third TSV is formed through the third substrate. For example, FIG. 2 shows some embodiments of a cross-sectional view corresponding to act 2006 and act 2008.

At 2010, the second substrate and the third substrate are bonded through the second TSV and the third TSV. For example, FIG. 3 shows some embodiments of a cross-sectional view corresponding to act 2010.

It will be appreciated that while reference is made throughout this document to exemplary structures in discussing aspects of methodologies described herein that those methodologies are not to be limited by the corresponding structures presented. Rather, the methodologies (and structures) are to be considered independent of one another and able to stand alone and be practiced without regard to any of the particular aspects depicted in the Figs. Additionally, layers described herein, can be formed in any suitable manner, such as with spin on, sputtering, growth and/or deposition techniques, etc.

In view of the foregoing, some embodiments of the present application provide a 3D IC. A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, the 3D IC comprises a first IC die comprising a first substrate, a first interconnect structure disposed over the first substrate, and a first through substrate via(TSV) disposed through the first substrate. The 3D IC further comprises a second IC die comprising a second substrate, a second interconnect structure disposed over the second substrate, and a second TSV disposed through the second substrate. The 3D IC further comprises a bonding structure arranged between back sides of the first IC die and the second IC die opposite to corresponding interconnect structures and bonding the first IC die and the second IC die. The bonding structure comprises conductive features disposed between and electrically connecting the first TSV and the second TSV.

Further, other embodiments of the present application provide another 3D IC. The 3D IC comprises a first IC die comprising a first substrate and a first interconnect structure over the first substrate, the first IC die having a front side and a back side opposite to the front side, wherein the first IC die comprises a first TSV (through substrate via) disposed through the first substrate. The 3D IC further comprises a second IC die comprising a second substrate and a second interconnect structure over the second substrate. The second IC die is bonded to the back side of the first IC die by a bonding structure that electrically connects a metal line of the second IC die to the first TSV.

Further yet, other embodiments of the present application provide another 3D IC. The 3D IC comprises a first IC die comprising a first substrate and a first interconnect structure over the first substrate, a second IC die comprising a second substrate, a first TSV disposed through the second substrate, and a second interconnect structure over the second substrate. The second IC die is bonded to the first IC die. The 3D IC further comprises a third IC die comprising a third substrate, a second TSV through the third substrate, and a third interconnect structure disposed over the third substrate and a fourth IC die comprising a fourth substrate and a fourth interconnect structure over the fourth substrate. The fourth IC die is bonded to the third IC die. The 3D IC further comprises a bonding structure comprising bonding conductive features bonding the second IC die and the third IC die and disposed between and electrically connecting the first TSV and the second TSV.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A three-dimensional (3D) integrated circuit (IC) comprising: a first IC die comprising a first substrate, a first interconnect structure disposed over the first substrate, and a first through substrate via(TSV) disposed through the first substrate; a second IC die comprising a second substrate, a second interconnect structure disposed over the second substrate, and a second TSV disposed through the second substrate; and a bonding structure arranged between back sides of the first IC die and the second IC die opposite to corresponding interconnect structures and bonding the first IC die and the second IC die, the bonding structure comprising conductive features disposed between and electrically connecting the first TSV and the second TSV.
 2. The 3D IC according to claim 1, wherein the bonding structure further comprises a bonding dielectric layer disposed directly on a back side of the first substrate, surrounding the conductive features, and contacting the first TSV.
 3. The 3D IC according to claim 2, wherein the conductive features comprise a metal line disposed in the bonding dielectric layer.
 4. The 3D IC according to claim 3, wherein the conductive features further comprise a metal via disposed in the bonding dielectric layer and connecting the metal line and the first TSV.
 5. The 3D IC according to claim 3, wherein the metal line directly contacts the second TSV.
 6. The 3D IC according to claim 3, wherein the conductive features further comprise a redistribution layer disposed in the bonding dielectric layer between the metal line and the second TSV.
 7. The 3D IC according to claim 1, wherein the conductive features comprise a pair of metal vias respectively disposed in a first bonding dielectric layer and a second bonding dielectric layer arranged between the first TSV and the second TSV.
 8. The 3D IC according to claim 7, wherein the conductive features further comprise a pair of metal lines respectively disposed in the first bonding dielectric layer and the second bonding dielectric layer arranged between the pair of metal vias.
 9. The 3D IC according to claim 8, wherein the conductive features further comprise a pair of redistribution layers disposed in the first bonding dielectric layer and the second bonding dielectric layer between the pair of metal lines.
 10. The 3D IC according to claim 9, wherein the pair of metal lines is respectively in direct contact with the pair of redistribution layers.
 11. The 3D IC according to claim 9, wherein the pair of metal lines is respectively connected to the pair of redistribution layers through an additional pair of metal vias.
 12. The 3D IC according to claim 1, wherein the first interconnect structure comprises a first plurality of metal lines and a first plurality of metal vias alternatingly stacked in a first ILD layer (interlayer dielectric layer); and wherein the second interconnect structure comprises a second plurality of metal lines and a second plurality of metal vias alternatingly stacked in a second ILD layer; and wherein the first TSV is disposed overlying the first interconnect structure reaching on one of the first plurality of metal lines closest to the first substrate; and wherein the second TSV is disposed overlying the second interconnect structure reaching on one of the second plurality of metal lines closest to the second substrate.
 13. A three-dimensional (3D) integrated circuit (IC) comprising: a first IC die comprising a first substrate and a first interconnect structure over the first substrate, the first IC die having a front side and a back side opposite to the front side, wherein the first IC die comprises a first TSV (through substrate via) disposed through the first substrate; and a second IC die comprising a second substrate and a second interconnect structure over the second substrate, wherein the second IC die is bonded to the back side of the first IC die by a bonding structure that electrically connects a metal line of the second IC die to the first TSV.
 14. The 3D IC according to claim 13, wherein the bonding structure comprises a conductive feature disposed within a bonding dielectric layer, electrically connected to the metal line, and bonded to the first TSV.
 15. The 3D IC according to claim 14, wherein the conductive feature comprises a bonding contact electrically connected to the metal line of the second IC die directly bonded to the first TSV.
 16. The 3D IC according to claim 14, wherein the conductive feature comprises redistribution layer bonded directly to the first TSV and electrically connected to the metal line of the second IC die through a metal via.
 17. The 3D IC according to claim 14, wherein the conductive feature comprises a bonding contact of the first IC die electrically connected to the first TSV and bonded directly to the metal line of the second IC die.
 18. The 3D IC according to claim 14, wherein the conductive feature comprises a pair of bonding contacts bonded to one another and disposed between the first TSV and the metal line of the second IC die.
 19. The 3D IC according to claim 13, wherein the first TSV is directly bonded to the metal line of the second IC die.
 20. A three-dimensional (3D) integrated circuit (IC), comprising: a first IC die comprising a first substrate and a first interconnect structure over the first substrate; a second IC die comprising a second substrate, a first TSV disposed through the second substrate, and a second interconnect structure over the second substrate, wherein the second IC die is bonded to the first IC die; a third IC die comprising a third substrate, a second TSV through the third substrate, and a third interconnect structure disposed over the third substrate; a fourth IC die comprising a fourth substrate and a fourth interconnect structure over the fourth substrate, wherein the fourth IC die is bonded to the third IC die; and a bonding structure comprising bonding conductive features bonding the second IC die and the third IC die and disposed between and electrically connecting the first TSV and the second TSV. 